1. Field of the Invention
The present invention relates to the structure of a semiconductor device having a transistor. In particular, the present invention relates to the structure of an active matrix type semiconductor device having a thin film transistor (hereinafter referred to as TFTs) manufactured on an insulator such as glass and plastic. Further, the present invention relates to electronic equipment using this type of semiconductor device as a display portion.
2. Description of the Related Art
In recent years, the development of display devices using a light emitting element such as an electroluminescence (EL) element has become active. A light emitting element emits light by itself, and thus, has high visibility. The light emitting element does not need a backlight necessary for a liquid crystal display device (LCD), which is suitable for a reduction of a light emitting device in thickness. Also, the light emitting element has no limitation on a viewing angle.
The term EL element indicates an element having a light emitting layer in which luminescence generated by the application of an electric field can be obtained. There are a light emission when returning to a base state from a singlet excitation state (fluorescence), and a light emission when returning to a base state from a triplet excitation state (phosphorescence) in the light emitting layer, and a semiconductor device of the present invention may use either of the aforementioned types of light emission.
EL elements normally have a laminate structure in which a light emitting layer is sandwiched between a pair of electrodes (anode and cathode). A laminate structure having “an anode, a hole transporting layer, a light emitting layer, an electron transporting layer, and a cathode”, proposed by Tang et al. of Eastman Kodak Company, can be given as a typical structure. This structure has extremely high efficiency light emission, and most of the EL elements currently being researched employ this structure.
Further, structures having the following layers laminated in order between an anode and a cathode also exist: a hole injecting layer, a hole transporting layer, a light emitting layer, and an electron transporting layer; and a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer. Any of the above-stated structures may be employed as the EL element structure used in the semiconductor device of the present invention. Furthermore, fluorescent pigments and the like may also be doped into the light emitting layer.
All layers formed in EL elements between the anode and the cathode are referred to generically as “EL layers” in this specification. The aforementioned hole injecting layer, hole transporting layer, light emitting layer, electron transporting layer, and electron injecting layer are all included in the category of EL layers, and light emitting elements structured by an anode, an EL layer, and a cathode are referred to as EL elements.
FIG. 3 shows a configuration of a pixel in a general semiconductor device. Note that, for example, an EL display device is used as a typical semiconductor device. The pixel shown in FIG. 3 has a source signal line 301, a gate signal line 302, a switching TFT 303, a driving TFT 304, capacitor means 305, an EL element 306, a current supply line 307, and a power source line 308.
A connection relationship among the respective elements will be described. Here, a TFT has three terminals of a gate, a source and a drain. However, with respect to the source and the drain, both cannot be clearly distinguished because of a structure of the TFT. Thus, when the connection among elements is described, one of the source and the drain represents a first electrode and the other represents a second electrode. When the description of potentials of the respective terminals (voltage between the gate and the source of a TFT, or the like) or the like is required with respect to ON and OFF of a TFT, for example, the source and the drain are indicated.
Also, in this specification, turning ON of a TFT indicates a state in which a voltage between the gate and source of the TFT exceeds a threshold value thereof and a current flows between the source and the drain. In addition, turning OFF of a TFT indicates a state in which a voltage between the gate and source of the TFT becomes lower than a threshold value thereof and a current does not flow between the source and the drain.
The gate electrode of the switching TFT 303 is connected with the gate signal line 302, the first electrode thereof is connected with the source signal line 301, and the second electrode thereof is connected with the gate electrode of the driving TFT 304. The first electrode of the driving TFT 304 is connected with the current supply line 307 and the second electrode thereof is connected with the first electrode of the EL element 306. The second electrode of the EL element 306 is connected with the power source line 308. The capacitor means 305 is connected between the gate electrode of the driving TFT 304 and the first electrode thereof and holds a voltage between the gate and the source of the driving TFT 304.
When a potential on the gate signal line 302 is changed to turn ON the switching TFT 303, a video signal inputted to the source signal line 301 is inputted to the gate electrode of the driving TFT 304. A voltage between the gate and the source of the driving TFT 304 is determined according to a potential of the inputted video signal so that a current flowing between the source and the drain of the driving TFT 304 (hereinafter referred to as a drain current) is determined. The current is supplied to the EL element 306 to emit light.
Now, a TFT made of polycrystalline silicon (polysilicon, hereinafter referred to as P-Si) has higher field effect mobility than a TFT made of amorphous silicon (hereinafter referred to as A-Si) and a larger ON current than that. Thus, it is more suitable as a transistor used for a semiconductor device.
On the other hand, with respect to the TFT made of polysilicon, there is a problem in that variations in electrical characteristics are easy to cause by a defect in a grain boundary.
In the pixel shown in FIG. 3, when characteristics such as a threshold value and an ON current of a TFT composing the pixel are varied for each pixel, even in the case where the same video signal is inputted, an amount of a drain current of the TFT is changed according thereto so that the intensity of the EL element 306 is varied. Thus, in the case of analog gradation, it becomes a problem.
Therefore, a digital gradation method of driving an EL element with only two states in which the intensity is 100% and 0% using a region in which a threshold value of a TFT or the like is hard to influence an ON current is proposed. According to this method, only two gray levels of white and black can be expressed. Thus, it is combined with a time gradation method or the like so that multi-gradation is realized.
When a method in which the digital gradation method is combined with the time gradation method is used, as configurations of a pixel in a semiconductor device, there are configurations shown in FIGS. 4A and 4B. When a canceling TFT 406 is used in addition to the switching TFT 404 and the driving TFT 405, it is possible to sensitively control a length of a light emitting time.
On the other hand, an example of a configuration capable of correcting a variation in threshold value of a TFT using another method is proposed in SID 98 DIGEST P11 “Design of an Improved Pixel for a Polysilicon Active-Matrix Organic LED Display”. As shown in FIGS. 5A and 5B, it has a source signal line 501, first to third gate signal lines 502 to 504, TFTs 505 to 508, capacitor means 509 (C2) and 510 (C1), an EL element 511, and a current supply line 512.
The gate electrode of the TFT 505 is connected with the first gate signal line 502, the first electrode thereof is connected with the source signal line 501, and the second electrode thereof is connected with the first electrode of the capacitor means 509. The second electrode of the capacitor means 509 is connected with the first electrode of the capacitor means 510. The second electrode of the capacitor means 510 is connected with the current supply line 512. The gate electrode of the TFT 506 is connected with the second electrode of the capacitor means 509 and the first electrode of the capacitor means 510, the first electrode thereof is connected with the current supply line 512, and the second electrode thereof is connected with the first electrode of the TFT 507 and the first electrode of the TFT 508. The gate electrode of the TFT 507 is connected with the second gate signal line 503 and the second electrode thereof is connected with the second electrode of the capacitor means 509 and the first electrode of the capacitor means 510. The gate electrode of the TFT 508 is connected with the third gate signal line 504 and the second electrode thereof is connected with the first electrode of the EL element 511. The second electrode of the EL element 511 is supplied with a predetermined potential through a power source line 513 so that there is a potential difference between the second electrode and the current supply line 512.
The operation will be described using FIG. 5B and FIGS. 6A to 6F. FIG. 5B shows timing of a video signal and pulses which are inputted to the source signal line 501 and the first to third gate signal lines 502 to 504, and timing is divided into sections of I to VIII according to the respective operations shown in FIGS. 6A to 6F. In addition, according to the example of the pixel shown in FIG. 5A, it is composed of four TFTs and their polarities each are a P-channel type. Thus, when an L level is inputted to the gate electrode, it is turned ON. When an H level is input, it is turned OFF.
First, the first gate signal line 502 becomes an L level so that the TFT 505 is turned ON. At this time, the third gate signal line is an L level so that the TFT 508 is in an ON state (section I). Subsequently, the second gate signal line becomes an L level so that the TFT 507 is turned ON. Here, as shown in FIG. 6A, the capacitor means 509 and 510 are charged. Then, when a voltage held by the capacitor means 510 exceeds a threshold value (Vth) of the TFT 506, the TFT 506 is turned ON (section II).
Subsequently, the third gate signal line becomes an H level so that the TFT 508 is turned OFF. Then, charges stored in the capacitor means 509 and 510 move again, and soon a voltage held by the capacitor means 510 becomes equal to Vth. At this time, as shown in FIG. 6B, respective potentials on the current supply line 512 and the source signal line 501 are VDD. Thus, even in the capacitor means 509, a held voltage becomes equal to Vth. Accordingly, the TFT 506 is turned OFF soon.
As described above, when voltages held by the capacitor means 509 and 510 become equal to Vth, the second gate signal line 503 becomes an H level so that the TFT 507 is turned OFF (section IV). By such operations, as shown in FIG. 6C, Vth is held in the capacitor means.
At this time, with respect to a charge Q1 stored in the capacitor means 510 (C1), a relation indicated by Equation 1 is held. Simultaneously, with respect to a charge Q2 stored in the capacitor means 509 (C2), a relation indicated by Equation 2 is held.
                              Q          1                =                              C            1                    ×                                                V              th                                                                      (                  Equation          ⁢                                          ⁢          1                )            
                              Q          2                =                              C            2                    ×                                                V              th                                                                      (                  Equation          ⁢                                          ⁢          2                )            
Subsequently, as shown in FIG. 6D, a video signal is inputted (section V). The video signal is outputted to the source signal line 501 and its potential is changed from VDD to a potential of the video signal VData (here, assume that VDD>VData because the TFT 506 is a P-channel type). At this time, when a potential of the gate electrode of the TFT 506 is given by Vp and a charge in the node is given by Q, relations indicated by Equations 3 and 4 are held from charge conservation law, including the capacitor means 509 and 510.
                              Q          +                      Q            1                          =                              C            1                    ×                      (                                          V                                  D                  ⁢                                                                          ⁢                  D                                            -                              V                P                                      )                                              (                  Equation          ⁢                                          ⁢          3                )            
                              Q          -                      Q            2                          =                              C            2                    ×                      (                                          V                P                            -                              V                DATA                                      )                                              (                  Equation          ⁢                                          ⁢          4                )            
Based on Equations 1 to 4, the potential Vp of the gate electrode of the TFT 506 is indicated by Equation 5.
                              V          P                =                                                            C                1                                                              C                  1                                +                                  C                  2                                                      ⁢                          V                              D                ⁢                                                                  ⁢                D                                              +                                                    C                2                                                              C                  1                                +                                  C                  2                                                      ⁢                          V              DATA                                -                                                V              th                                                                      (                  Equation          ⁢                                          ⁢          5                )            
Thus, a voltage VGS between the gate and the source of the TFT 506 is indicated by Equation 6.
                                                                        V                                  G                  ⁢                                                                          ⁢                  S                                            =                                                V                  P                                -                                  V                                      D                    ⁢                                                                                  ⁢                    D                                                                                                                          =                                                                                          C                      2                                                                                      C                        1                                            +                                              C                        2                                                                              ⁢                                      (                                                                  V                        DATA                                            -                                              V                                                  D                          ⁢                                                                                                          ⁢                          D                                                                                      )                                                  -                                                                        V                    th                                                                                                                                            =                                                                                          C                      2                                                                                      C                        1                                            +                                              C                        2                                                                              ⁢                                      (                                                                  V                        DATA                                            -                                              V                                                  D                          ⁢                                                                                                          ⁢                          D                                                                                      )                                                  +                                  V                  th                                                                                        (                  Equation          ⁢                                          ⁢          6                )            
The term of Vth is included in the right side of Equation 6. In other words, the threshold value of the TFT 506 in the pixel is added to the video signal inputted from the source signal line and the resultant signal is held by the capacitor means 510.
When the input of the video signal is completed, the first gate signal line 502 becomes an H level so that the TFT 505 is turned OFF (section VI). After that, the source signal line is returned to a predetermined potential (section VII). By the above operation, write operation of the video signal into the pixel is completed (FIG. 6E).
Subsequently, the third gate signal line becomes an L level so that the TFT 508 is turned ON. Thus, as shown in FIG. 6F, a current flows into the EL element so that the EL element emits light. At this time, a value of the current flowing into the EL element depends on a voltage between the gate and the source of the TFT 506 and a drain current IDS flowing into the TFT 506 is indicated by Equation 7.
                                                                        I                                  D                  ⁢                                                                          ⁢                  S                                            =                                                β                  2                                ⁢                                                      (                                                                  V                                                  G                          ⁢                                                                                                          ⁢                          S                                                                    -                                              V                        th                                                              )                                    2                                                                                                        =                                                β                  2                                ⁢                                                      {                                                                                            C                          2                                                                                                      C                            1                                                    +                                                      C                            2                                                                                              ⁢                                              (                                                                              V                            DATA                                                    -                                                      V                                                          D                              ⁢                                                                                                                          ⁢                              D                                                                                                      )                                                              }                                    2                                                                                        (                  Equation          ⁢                                          ⁢          7                )            
From Equation 7, it is apparent that the drain current IDS of the TFT 506 does not depend on the threshold value Vth. Thus, even in the case where the threshold value of the TFT 506 is varied, the value is corrected for each pixel and added to the video signal. Accordingly, it is apparent that a current depending on the potential VDATA of the video signal flows into the EL element.
However, in the case of the above configuration, when capacitance values of the capacitor means 509 and 510 are varied, the drain current IDS of the TFT 506 is varied.